PHOENICS research is foundational in striving to create the blueprint for future photonic compute systems in a post-von-Neumann computing era.

PHOENICS stands for “Photonic enabled petascale in-memory computing with femtojoule energy consumption” and sums up the three goals of the project:

in-memory computing will allow data processing more similar to the human brain by removing the separation between computing and data storage units;

photonic technology will provide high speed data transport where current electronic systems face severe limitations;

photonic computing will lead to significant energy ad-vantages.

Modern digital electronic technologies struggle with the enormous amount of generated and processed data. A growing gap arises between needs and capabilities of today’s information technology infrastructure. Conventional approaches based on electrical data processing are limited by the parameters of bandwith because of connectivity demands, latency because of sequential operation, and power efficiency because compute density does not scale linearly with the number of inputs. 

By switching to the optical domain and nanophotonic circuits PHOENICS will set a new paradigm in AI and neuromorphic computing:  

Photonic interconnects can directly address the data transport problem: most of the energy on a modern microelectronic chip is consumed charging and discharging metal wires. Photonic systems can utilize optical multiplexing and high speed signals to achieve ultrahigh bandwidth density. This translates to a very high computational density (ops/s/mm2).

Energy efficiency: Implementing linear operations such as multiply-accumulate (MAC) in the photonic domain does not intrinsically consume any significant energy.

The PHOENICS project aims to establish neuromorphic photonic hardware to realize next generation compute platforms for AI.


PHOENICS architecture based on a hybrid integration of a micro comb chip, InP active modulation unit, complemented with photonics MVM processing unit

The PHOENICS architecture is based on the hybrid integration approach of three different chip platforms:optical input generation in silicon nitride signal encoding and modulation in indium phosphideneuromorphic proces-sing and detection in silicon.

The chip module for generating the optical driving signals will be developed jointly by EPFL and MicroR Systems using chip-scale optical frequency combs operating in the soliton regime (soliton microcombs). The PHOENICS project will employ coherent frequency microcombs as the ultimate integrated sources aligned to the telecom ITU grid. This approach will enable the generation of spectrally precisely aligned wavelength channels in a compact format.

HHI will develop an InP (indium phosphide) module as the active modulation unit for encoding the input vectors for neuromorphic processing. This module will provide modulated and multiplexed input signals for matrix processing. The InP module will consist of high-speed electro-absorption modulators delivering up to 20 GHz modulation speed.

The optically encoded vectors will be processed by an ultrafast matrix-vector-multiplication (MVM) processor. The MVM chip will be realized using silicon photonics technology developed jointly by the Universities of Exeter, Oxford, and Ghent.

WWU, Nanoscribe GmbH & Co. KG, and IBM will design the system architecture and join the chip platforms.



will radically improve existing technology for neuromorphic computing;

provides a disruptive hardware platform for energy efficient neuromorphic processing with enormous potential for further energy savings;

will develop novel strategies for joining key photonic foundry platforms in hybrid systems.

Ultra low loss SI3N4 integrated photonic circuits for comb generation (EPFL).